output            conv_en,
	reg            conv_en_func;
	input             test_config_dft,
	input             test_conv_start,           //external conv_en in test_config_dft
	
	assign conv_en = conv_en_func | ( test_conv_start & test_config_dft ) ; 
	
	/*******************************/
	
	reg  sleep_adc_trigger_req_tmp  ;
reg sleep_adc_trigger_req_sync ;
reg sleep_adc_trigger_req_sync_pred ;

always @ (posedge clk or negedge reset_b) begin
   if (!reset_b) 
   begin   
      exit_from_sleep_detected        <= 1'b0;
      sleep_adc_trigger_req_tmp       <= 1'b1;
      sleep_adc_trigger_req_sync      <= 1'b1;
      sleep_adc_trigger_req_sync_pred <= 1'b1;
   end 
   else begin
      sleep_adc_trigger_req_tmp <= !oscslp_conf ? sleep_adc_trigger_req  :  !sleep_mode_deb ;
          
      sleep_adc_trigger_req_sync <= sleep_adc_trigger_req_tmp;
      sleep_adc_trigger_req_sync_pred  <=  sleep_adc_trigger_req_sync ;
 
      if (sleep_adc_trigger_req_sync  && !sleep_adc_trigger_req_sync_pred )
         exit_from_sleep_detected <= 1'b1;
      else 
         exit_from_sleep_detected <= 1'b0;
   end
end

*///////////////////////////////

http://www.chipverify.com/verilog/positive-edge-detector-verilog

module pos_edge_det ( input sig,
                      input clk,
                      output pe);
 
  reg   sig_dly;
 
  always @ (posedge clk) begin
    sig_dly <= sig;
  end
 
  assign pe = sig & ~sig_dly;
endmodule 




	wire signal_in;
wire edge_detected;
reg signal_d;

always @(posedge clk or negedge rst_n)
begin
if (~rst_n)
signal_d <= #1 1'b0;
else
signal_d <= #1 signal_in;
end

assign edge_detected = signal_in & (~signal_d);





module FED(in,clk,out);
input in,clk;
output out;
wire q0,q1;
D_FF D1(in,clk,q0), //instantiation of D Flip Flop
D2(q0,clk,q1);
assign out=(q0 && !q1);
endmodule

module D_FF(d,clk,q); //D Flip Flop module
input d,clk;
output reg q;
always@(negedge clk)
begin
q<=d;
end
endmodule



module control
(
    output logic pcEn,
    input clock, ready
);
    reg r1, r2, r3;

    always @(posedge clock) begin
        r1 <= ready;    // first stage of 2-stage synchronizer
        r2 <= r1;       // second stage of 2-stage synchronizer
        r3 <= r2;       // edge detector memory
    end

    pcEn <= r2 && !r3;   // pulse on rising edge
endmodule



https://books.google.fr/books?id=aQd4QYNV88EC&pg=PA11&lpg=PA11&dq=verilog+rising+edge+detect+example&source=bl&ots=f-8kWLIWGS&sig=UJUZDOpyYzfiy3r_iq0GP7qF9SM&hl=fr&sa=X&ved=0ahUKEwjRt8DEjfHXAhXnD8AKHbstChw4ChDoAQhXMAY#v=onepage&q=verilog%20rising%20edge%20detect%20example&f=false

pour changer la fréquence de l'adc de 1us a 2us soit 500Khz

input          clk_42p6us_en,
input          clk_85p3us_en,
input          clk_170p6us_en,
input          clk_682p6us_en,
input          i2c_sel,
input [1:0]    conv_period,

reg         refresh_clk_en;

// -----------------------------------------------------------------------------
// i2c periodic conv counter - refresh period 2ms  
// -----------------------------------------------------------------------------
// adc VIT conversion refresh period progammable by i2c
  always @ (*) begin
     case (conv_period )
        2'b00:  refresh_clk_en = clk_682p6us_en ;  //conv period= 10ms
        2'b01:  refresh_clk_en = clk_170p6us_en;   //conv period= 2ms
        2'b10:  refresh_clk_en = clk_85p3us_en;    //conv period= 1ms
        2'b11:  refresh_clk_en = clk_42p6us_en;    //conv period= 500us
      endcase  
  end
   
   
   
   
   assign adc_clk_en =  fsm_clk_en | serial_clk_en;

always @ (*) begin
    case ( adc_clk_freq )
    2'b00 : adc_clk_sel = adc_clk2_en;       //750khz  
    2'b01 : adc_clk_sel = adc_clk_en ;       //3Mhz          
    2'b10 : adc_clk_sel = adc_clk1_en;       //1.5Mhz        
    2'b11 : adc_clk_sel = adc_clk3_en;       //375khz       
    endcase
end

dig_cgc cgc_adc_clk   ( .clkout( adc_clk_int ), .clkin( adc_clk_in ), .en( adc_clk_sel & adc_clk_en ), .se( scan_en ) );

assign adc_clk = ( !scan_mode && test_config_dft ) ? adc_ext_clk : adc_clk_int;

assign en_adc = en_adc_start | en_adc_fsm;



	$display("\n enter test_mode");
   i2c_master.i2cWr(8'd126,8'h17);
   i2c_master.i2cWr(8'd126,8'h51);

   $display("\n verify test_mode");
   i2c_test_mode_sns_fld = 1;
   i2c_read_fields(`TEST_REGISTER0,8'hf8);
         
   $display("\n enter ADC DFT config");
   i2c_tb_adc_dft_config_fld = 1'b1;
   i2c_tb_adc_ext_vref_fld = 1'b1;
   i2c_tb_adc_channel_fld = 3;
   i2c_write_fields(fnGetAddr("i2c_tb_adc_dft_config_fld"));   
   #100;
   check_digital_net_id("cli_in_en",cli_in_en,1'b1);
   check_digital_net_id("mode_in_en",mode_in_en,1'b1); 
    
   $display("\n run conversion for channel 4");     
   i2c_adc_manual_fld = 1'b1;
   i2c_adc_request_fld =1'b1;    
   i2c_write_fields(fnGetAddr("i2c_adc_request_fld"));   
   #1_000; //resynchro



dans regs 

	 .adc_manual                  ( adc_manual_reg ),         
 .tb_adc_dft_config           ( tb_adc_dft_config ),
    .tb_adc_signed               ( tb_adc_signed ),
    .tb_adc_channel              ( tb_adc_channel ),
    .tb_adc_ext_vref             ( tb_adc_ext_vref ),